This invention relates to a programmable logic array which can be used as a memory circuit for performing a combinational circuit or a sequential circuit and particularly to a rewritable programmable logic array which can be applied to various circuits as an associative memory or functional memory.
In the light of rapid development of LSI semiconductor memories, design engineers have been prompted to apply similar technology also to the design of general purpose logic networks capable of performing both combinational and sequential logic functions. Though the use of memory devices as Random Access Memory (RAM) or Read Only Memory (ROM) to implement logic, it is pointed out that as the number of input variables n grows larger the memories are inefficient in providing 2.sup.n word lines to implement n variable function regardless of the complexity of the function [see reference 1 cited in the appendix].
A programmable logic Array (PLA), which generally consists of a SEARCH array performing AND function and a READ array performing OR function, has been recognized as a memory device to realize combinational and sequential logic networks [see reference 1-3 cited in the appendix].
A brief description of a drawing of a prior art device is shown as follows.
FIG. 1 shows a diagram of a general Programmable Logic Array (PLA).
FIG. 2 is a 2-bit adder used as an example circuit of PLA representation.
FIG. 3 depicts a PLA representation of the 2-bit adder in FIG. 2.
FIG. 4 represents a read-only type of a bipolar PLA and FIG. 5 shows a diagram of a read/write type of prior art PLA with the complexity of the cell construction.
As shown in FIG. 1, a Programmable Logic Array (PLA) is based on the so-called naked PLA which consists of a SEARCH array and a READ array. When p-bit decoders are used as the bit partitioning networks in a general symmetric PLA, the number of the partitioned bit lines, N, and the number of cells, S.sub.p, are given respectively as follows: EQU N=2.sup.p .times.(n/p) (1) EQU S.sub.p =l.times.(N+m) (2)
Here, n,m and l are the number of input lines, output lines and word lines respectively in the PLA.
As the circuit example for the PLA representation, the 2-bit adder shown in FIG. 2 is used in this invention. The 2-bit adder accepts four input variables X.sub.0, X.sub.1, X.sub.2 and X.sub.3, and generates outputs F.sub.0, F.sub.1 and C.sub.out, which are the zero-order and first-order sums and a carry respectively. The three Boolean equations for F.sub.0, F.sub.1 and C.sub.out may be written as EQU F.sub.0 =X.sub.1 .crclbar.X.sub.0 ( 3) EQU F.sub.1 =(X.sub.1 .multidot.X.sub.0).crclbar.X.sub.2 .crclbar.X.sub.3 ( 4) EQU C.sub.out =X.sub.3 .multidot.X.sub.2 .multidot.(X.sub.1 .multidot.X.sub.0 VX.sub.3 .crclbar.X.sub.2) (5)
where the symbols .multidot., V, .crclbar. and .sup.- represent the operations of AND, OR, EXCLUSIVE-OR and INVERT respectively.
The PLA representation of the 2-bit adder is shown in FIG. 3. Two 2-bit decoders are used as the bit partitioning networks.
Let B.sub.i (i=0,1, . . . ,7), W.sub.j (j=0,1,2,3) and Z.sub.k (k=0,1,2) be Boolean variables for bit lines b.sub.i, word lines w.sub.j and output bit lines z.sub.k respectively, W.sub.j and Z.sub.k are given by ##EQU1##
Compared with the RAM or the ROM, the PLA is expected to be more efficient in its silicon area requirements, though the cell number of the PLA varies drastically as a function of the partitioning for the input decorders [see reference 1 cited in the appendix].
Historically, a read-only type of PLA, which generates specific Boolean output functions by open-circuiting or short-circuiting some cells at intersections of bit lines and word lines on the array, has been widely used in the market as a Field-PLA or a Mask-PLA.
But, for a read/write type of PLA, the ideal memory cell to perform the `bit personality` to realize specific logic functions [see reference 1 cited in the appendix] and to be rewritable easily is not yet available, though the concepts are already proposed as a functional memory [see reference 2 cited in the appendix] with writable storage cells capable of holding a binary 1, a binary 0 and a DON'T CARE, or a PLA [see reference 1 cited in the appendix] with use of small memory cell and NAND gate at each intersection of bit lines and word lines. The latter PLA is shown in FIG. 5. But, such a PLA is inefficient in the complexity of the cell constructions And interconnections. Also, I proposed in Japanese patent application No. 53-78411 filed on June, 1978 that a rewritable PLA can be constructed by using simplified Current Mode Logic (CML) memory cells. But, the disadvantage of the rewritable PLA is in that in the SEARCH part bit personalities to realize specific logic functions can not be written from the work direction.